On Tue, Apr 30, 2019 at 7:13 AM Geert Uytterhoeven <geert+renesas@xxxxxxxxx> wrote: > > Add DT bindings for the Renesas RZ/A1 Interrupt Controller. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- > v2: > - Add "renesas,gic-spi-base", > - Document RZ/A2M. > --- > .../renesas,rza1-irqc.txt | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt > new file mode 100644 > index 0000000000000000..ea8ddb6955338ccd > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt > @@ -0,0 +1,30 @@ > +DT bindings for the Renesas RZ/A1 Interrupt Controller > + > +The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas > +RZ/A1 and RZ/A2 SoCs: > + - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI > + interrupts, > + - NMI edge select. > + > +Required properties: > + - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as > + fallback. > + Examples with soctypes are: > + - "renesas,r7s72100-irqc" (RZ/A1H) > + - "renesas,r7s9210-irqc" (RZ/A2M) > + - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined > + in interrupts.txt in this directory) > + - interrupt-controller: Marks the device as an interrupt controller > + - reg: Base address and length of the memory resource used by the interrupt > + controller > + - renesas,gic-spi-base: Lowest GIC SPI interrupt number this block maps to. Why isn't this just an 'interrupts' property? Plus, without 'interrupts' walking the hierarchy is broken. Rob
