Hi Simon, On Mon, Apr 08, 2019 at 10:31:48AM +0200, Simon Horman wrote: > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of > August 24, 2018, the TX clock internal delay mode isn't supported > on R-Car E3 (r8a77990) and D3 (r8a77995). > > * TX clock internal delay mode is required for reliable 1Gbps communication > using the KSZ9031RNX phy present on the Ebisu and Draak boards. > > Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and > the speed should be limited to 100Mbps. "cannot" missing? > Based on work by Kazuya Mizuguchi. > > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx> > --- > arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 + > arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 + > 2 files changed, 2 insertions(+) > > Based on renesas-devel-20190404-v5.1-rc3 > > diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts > index c72772589953..05214b8dd2c5 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts > +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts > @@ -272,6 +272,7 @@ > interrupt-parent = <&gpio2>; > interrupts = <21 IRQ_TYPE_LEVEL_LOW>; > reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; > + max-speed = <100>; What about adding a comment explaining this speed limit? Thanks, Wolfram
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