Re: [PATCH v6 0/7] clk: renesas: r8a77990, r8a774c0: Add Z2 clock

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

Hi Simon,

On Mon, Mar 25, 2019 at 5:36 PM Simon Horman <horms+renesas@xxxxxxxxxxxx> wrote:
> this series adds the Z2 clock as a clock with both a fixed and variable
> divisor with a parent of PLL0 to the CPG-MSSR drivers for the R-Car E3
> (r8a77990) and RZ/G2E (r8a774c0) SoCs.

Thanks, queued in clk-renesas-for-v5.2, after dropping the extra semicolon
in patch 1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
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