On Thu, Feb 28, 2019 at 12:02:15PM +0100, Geert Uytterhoeven wrote:
> From: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@xxxxxxxxxxx>
>
> In accordance with hardware specification Ver 1.0, reset register
> transmission / reception setting before transfer.
>
> Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@xxxxxxxxxxx>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> ---
> drivers/spi/spi-sh-msiof.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
> index b20e70a2bdd115d7..6e83368874839d09 100644
> --- a/drivers/spi/spi-sh-msiof.c
> +++ b/drivers/spi/spi-sh-msiof.c
> @@ -130,6 +130,8 @@ struct sh_msiof_spi_priv {
> #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
> #define CTR_TXE 0x00000200 /* Transmit Enable */
> #define CTR_RXE 0x00000100 /* Receive Enable */
> +#define CTR_TXRST 0x00000002 /* Transmit Reset */
> +#define CTR_RXRST 0x00000001 /* Receive Reset */
nit: can we start using the BIT() macro here?
> /* FCTR */
> #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
> @@ -246,6 +248,25 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
> return IRQ_HANDLED;
> }
>
> +static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
> +{
> + u32 mask = CTR_TXRST | CTR_RXRST;
> + u32 data;
> + int k;
> +
> + data = sh_msiof_read(p, CTR);
> + data |= mask;
> +
> + sh_msiof_write(p, CTR, data);
> +
> + for (k = 100; k > 0; k--) {
> + if (!(sh_msiof_read(p, CTR) & mask))
> + break;
> +
> + udelay(1);
> + }
> +}
> +
> static const u32 sh_msiof_spi_div_array[] = {
> SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
> SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
> @@ -925,6 +946,9 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr,
> bool swab;
> int ret;
>
> + /* reset registers */
> + sh_msiof_spi_reset_regs(p);
> +
> /* setup clocks (clock already enabled in chipselect()) */
> if (!spi_controller_is_slave(p->ctlr))
> sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
> --
> 2.17.1
>
