Hello Sergei,
Thank you for your feedback!
> -----Original Message-----
> From: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
> Sent: 08 February 2019 12:53
> To: Simon Horman <horms+renesas@xxxxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; Magnus Damm <magnus.damm@xxxxxxxxx>; Fabrizio Castro
> <fabrizio.castro@xxxxxxxxxxxxxx>
> Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
>
> Hello!
>
> On 02/08/2019 02:13 PM, Simon Horman wrote:
>
> > From: Fabrizio Castro <fabrizio.castro@xxxxxxxxxxxxxx>
> >
> > This patch defines OOP tables for all CPUs, similarly to
> > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > R8A77990.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@xxxxxxxxxxxxxx>
> > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> [...]
> > @@ -55,6 +76,8 @@
> > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
>
> Need space after =...
Doh! Simon, do you want me to send another version to fix both spacing issues?
Thanks,
Fab
>
> > +operating-points-v2 = <&cluster1_opp>;
> > };
> >
> > a53_1: cpu@1 {
> > @@ -64,6 +87,8 @@
> > power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
>
>
> Here as well...
>
> > +operating-points-v2 = <&cluster1_opp>;
> > };
> >
> > L2_CA53: cache-controller-0 {
>
> MBR, Sergei
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