Hello Simon,
> From: Biju Das
> Sent: 30 January 2019 09:44
> Subject: RE: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider
>
> Hi Simon,
>
> Thanks for the patch
>
> > Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> > divider
> >
> > On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> > control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> > rather than the more common location bit[4:0].
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> > ---
> > drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> > gen3-cpg.c
> > index d21fdeb520e1..dfd2b9caeaf5 100644
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> > cpg_quirks_match[] __initconst = {
> > .soc_id = "r8a77990",
> > .data = (void *)Z2FC_BIT_MASK_SFT_8,
> > },
> > +{
> > +.soc_id = "r8a7745",
> > +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> > +},
> > { /* sentinel */ }
> > };
>
>
> RZ/G2E SoC id is r8a774c0.
+1
Cheers,
Fab
>
> Regards,
> Biju
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