On Wed, Jan 30, 2019 at 09:46:35AM +0000, Biju Das wrote:
> Hi Simon,
>
> Thanks for the patch
>
> > Subject: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable
> > clock
> >
> > On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock.
> > Rather it is a clock with:
>
> RZ/G2E SoC id is r8a774c0.
Sorry about that, somehow I got confused.
> > * A parent of CLK_PLL0 running at 4.8GHz
> > * A fixed divider of 4
> > * A variable divider controlled by the Z2FC bits of the RFQCRC register
> >
> > This can be described using the DEF_GEN3_Z with a clock type of
> > CLK_TYPE_GEN3_Z2.
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> > ---
> > drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > index 493874e5ebee..f2ea72d9d663 100644
> > --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > @@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[]
> > __initconst = {
> > DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,
> > CLK_PLL1_DIV2),
> > DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,
> > CLK_USB_EXTAL),
> >
> > -DEF_FIXED("z2", R8A7745_CLK_Z2,CLK_PLL0, 1, 1),
> > +DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z2,
> > CLK_PLL0, 4),
>
> Looks like wrong file name. it is supposed to be r8a774c0-cpg-mssr.c
>
> > DEF_FIXED("zg", R8A7745_CLK_ZG,CLK_PLL1, 6, 1),
> > DEF_FIXED("zx", R8A7745_CLK_ZX,CLK_PLL1, 3, 1),
> > DEF_FIXED("zs", R8A7745_CLK_ZS,CLK_PLL1, 6, 1),
> > --
> > 2.11.0
>
>
>
>
> Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
>
