On Mon, Jan 28, 2019 at 04:12:03PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Jan 28, 2019 at 3:01 PM Simon Horman <horms+renesas@xxxxxxxxxxxx> wrote:
> > Adds Z2 clock to CPG driver for the R-Car E3 (r8a77990) SoC.
> >
> > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> > @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
> > DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
> >
> > /* Core Clock Outputs */
> > + DEF_FIXED("z2", R8A77990_CLK_Z2, CLK_PLL0D4, 1, 1),
>
> According to R-Car Gen3 Hardware User's Manual rev. 1.50, the SYS-CPU
> Divider 2 is controlled through the Z2FC bit field in the Frequency
> Control Register C. So it is not a fixed clock, unlike on R-Car D3.
Thanks, I will look into that.
