On Tue, Jan 15, 2019 at 09:02:42PM +0900, Yoshihiro Kaneko wrote: > From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx> > > This patch define OOP tables for all CPUs. > This allows CPUFreq to function. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx> > --- Thanks, I have tested CPUFreq with this tested that with this patch and "[PATCH] clk: renesas: r8a77990: Add Z2 clock" (https://patchwork.kernel.org/patch/10783723/) applied on top of renesas-devel-20190128-v5.0-rc4. Geert, or others, is it expected that z2 does not scale in this test? # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor performance # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 800000 1000000 1200000 # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 # echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 # echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 # echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 # echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 > > This patch is based on the devel branch of Simon Horman's renesas tree. > > arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi > index 84bbe70..936714e 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi > @@ -55,6 +55,27 @@ > clock-frequency = <0>; > }; > > + cluster1_opp: opp_table10 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + }; > + opp-1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt = <820000>; > + clock-latency-ns = <300000>; > + opp-suspend; > + }; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -66,6 +87,8 @@ > power-domains = <&sysc R8A77990_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > }; > > a53_1: cpu@1 { > @@ -75,6 +98,8 @@ > power-domains = <&sysc R8A77990_PD_CA53_CPU1>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > }; > > L2_CA53: cache-controller-0 { > -- > 1.9.1 >
