Re: [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU

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On Mon, Jan 21, 2019 at 02:15:07PM +0100, Geert Uytterhoeven wrote:
> On Mon, Jan 21, 2019 at 2:14 PM Geert Uytterhoeven
> <geert+renesas@xxxxxxxxx> wrote:
> > According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
> > the parent clock of the DU module clocks on RZ/G2 is S1D1.
> 
> Oops, "RZ/G2E".

That aside,

Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>



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