On 1/18/19 8:41 AM, masonccyang@xxxxxxxxxxx wrote:
> Hi Marek,
Hi,
>> "Marek Vasut" <marek.vasut@xxxxxxxxx>
>> 2019/01/18 下午 03:10
>>
>> > +Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
>> > +----------------------------------------------------------
>> > +
>> > +Required properties:
>> > +- compatible: should be "renesas,rcar-gen3-rpc"
>> > +- #address-cells: should be 1
>> > +- #size-cells: should be 0
>> > +- reg: should contain three register areas:
>> > + first for the base address of rpc-if registers,
>> > + second for the direct mapping read mode and
>> > + third for the write buffer area.
>> > +- reg-names: should contain "regs", "dirmap" and "wbuf"
>> > +- clock-names: should contain "rpc"
>> > +- clocks: should contain 1 entries for the module's clock
>> > +
>> > +Example:
>> > +
>> > + rpc: rpc@ee200000 {
>> > + compatible = "renesas,rcar-gen3-rpc";
>> > + reg = <0 0xee200000 0 0x7fff>, <0 0x08000000 0 0x4000000>,
>>
>> 0x7fff should be 0x8000 , right ?
>
> RPC write buffer starts at 0xee208000 w/ 256 bytes size.
The size of the RPC-IF block is 0x8000 though, is it not ?
>> > + <0 0xee208000 0 0x100>;
>>
>> Isn't the write buffer part of the RPC-IF register set ?
>
> yep, but by Sergei and Geert's comments, we use a separate reg entry
> for this write buffer.
> ---- copy the replied email from Geert ---------------------------------
>> Maybe Geert or Marek could comment on it, thanks.
>
> Given the writer buffer is separate from the other registers (it's in
> a different
> 4 KiB page, and thus may be at a different offset on future SoCs), and not
> present on RZ/A1, I think it's a good idea to use a separate reg entry
> for it.
> -----------------------------------------------------------------------
+CC Chris, the RZ/A1 has no write buffer for the RPC ?
--
Best regards,
Marek Vasut
