Add SDHI3 UHS pin control and use it when enabling HS200 support
for SDHI3.
Based on work by Takeshi Kihara.
Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
---
Tested on top of renesas-devel-20190110-v5.0-rc1
[ 2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
[ 3.055659] mmc0: new HS400 MMC card at address 0001
[ 3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
[ 3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[ 3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[ 3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
[ 2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
[ 3.055659] mmc0: new HS400 MMC card at address 0001
[ 3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
[ 3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[ 3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[ 3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
[ 2.901527] renesas_sdhi_internal_dmac ee160000.sd: Linked as a consumer to regulator.2
[ 2.909824] renesas_sdhi_internal_dmac ee160000.sd: Linked as a consumer to regulator.1
[ 2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
[ 3.055659] mmc0: new HS400 MMC card at address 0001
[ 3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
[ 3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[ 3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[ 3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
128+0 records in
128+0 records out
134217728 bytes (134 MB) copied, 0.92438 s, 145 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 9.02486 s, 59.5 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 7.36003 s, 72.9 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 11.0156 s, 48.7 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 7.15907 s, 75.0 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 8.78869 s, 61.1 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 10.3861 s, 51.7 MB/s
The above test results seem favourable when compared to
testing against renesas-devel-20190110-v5.0-rc1 where the eMMC
device uses HS200 mode.
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 14.7343 s, 36.4 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 8.46809 s, 63.4 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 14.6945 s, 36.5 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 19.1677 s, 28.0 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 21.3139 s, 25.2 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 19.9205 s, 27.0 MB/s
---
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 89383aa35d65..f2846c9eb83f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -535,6 +535,12 @@
power-source = <1800>;
};
+ sdhi3_pins_uhs: sd3_uhs {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
@@ -689,12 +695,13 @@
&sdhi3 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi3_pins>;
- pinctrl-1 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_1p8v>;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
--
2.11.0
