On Thu, Nov 29, 2018 at 1:41 AM Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx> wrote: > On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400 > needs a quirk to function properly. The reason for the quirk is that > there are two settings which produces same divider value for the SDn > clock. On the effected boards the one currently selected results in > HS400 not working. > > This change uses the same method as the Gen2 CPG driver and simply > ignores the first clock setting as this is the offending one when > selecting the settings. Which of the two possible settings is used have > no effect for SDR104. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx> > > --- > * Changes since v1 > - Fixed spelling in commit message, thanks Sergei and Geert! > - Reworked the whole patch per Geerts suggestion. Instead of only > skipping the first row on the effected boards when setting the clock > rete totally ignore it. This is made possible by another change to the > clock driver posted separately from this series and which this patch > now depends on [1]. > > 1. [PATCH] clk: renesas: rcar-gen3: set state when registering SD clocks Thanks for the update! With s/rete/rate/: Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds