Hi Hoan-san, Thanks for your patch. On 2018-10-25 11:13:41 +0900, Nguyen An Hoan wrote: > From: Hoan Nguyen An <na-hoan@xxxxxxxxxxx> > > Fix setting value for IRQCTL register. We are setting the last 6 bits > of (IRQCTL) to be 1 (0x3f), this is only suitable for H3ES1.*, according > to new Hardware manual values 1 are "setting prohibited" for Gen3! Hum, as you point out this change is not suitable for H3 ES1.x so this would introduce a regression, which is not good. I will leave the final word to Wolfram but in my view you need to introduce quirk handling to keep support for H3 ES1.x or blacklist that SoC in the driver. > > Signed-off-by: Hoan Nguyen An <na-hoan@xxxxxxxxxxx> > --- > drivers/thermal/rcar_gen3_thermal.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c > index 7aed533..fde3fd8 100644 > --- a/drivers/thermal/rcar_gen3_thermal.c > +++ b/drivers/thermal/rcar_gen3_thermal.c > @@ -306,7 +306,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc) > > usleep_range(1000, 2000); > > - rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); > + rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); > rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); > rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2); > > -- > 2.7.4 > -- Regards, Niklas Söderlund
