Hi Jacopo, On Thursday, October 18, 2018, jacopo mondi wrote: > Here you define bindings that allows you to have only one > gpio-controller node for the whole system. Correct. Since DT describes HW, we do only have one gpio-controller for the entire chip. It is one piece of hardware, not many tiny pieces of hardware. > With RZ/A1 we have a gpio-controller sub-node for each port. As I started to write this driver, I think the RZ/A1 driver is a little bit strange. It is also one gpio-ctonroller HW. But, I'm not about to go suggesting we change the RZ/A1 driver any time soon. > It's > true though that you have a lot of ports and few pins per port, but > to refer to a gpio you have to index the gpio in the whole pin space > with RZA1_PIN_ID(): > > gpios = <&pinctrl RZA2_PIN_ID(P6, 0) GPIO_ACTIVE_HIGH>; > > While I think this is nicer: > gpios = <&port6 0 GPIO_ACTIVE_HIGH>; Both seem just as easy to use. The difference is I don't want lots and lots of device tree sub nodes that are not really needed. Technically, the GPIO controller is a single piece of HW that you index into it what pin you want to control. The 'indexing' is basically registers and bits addresses. But, it is still one big controller (not many smaller controllers like channels of SPI, UART or I2C). > Having gpio-controller sub-nodes also allows you > to specify a 'ngpios' property for each port (or do all ports have 8 > pins? If I read Table 51.1 right they don't..), The "controller" (actual HW) controls 8-pins per port. In the RZ/A2M, not all pins are hooked up to actual pin pads. And that also change with different packages like you mentioned. > and when RZ/A2x will > come and has different pins per port it's > easy for developers to identify the differences (but this > depends on the package too, so it's not that easy as I'm putting it > here probably) Yes, as you start to guess about different packages, an RZ/A2x, or even a RZ/A3, and all the different combinations, it gets complicated. However, what will always be true is that this pin controller HW, no matter what SoC it is in, will always have the ability to control 8 pins per port. So you just have to specify how many ports it has, and then that will be a correct description of the hardware. Chris
