Hello Shimoda-San and all,
RZ/G1C USB2.0 host/function controller has the below features compared to R-Car Gen2/Gen3 USB2.0 block
1) It has a shared pll reset register for hsusb0/hsusb1 and this register reside in hsusb0 block.
2) This implies, in order to enable USB1 host/peripheral, we need to enable hsusb0 block as well.
3) USB2.0 Host controller block is similar to R-Car Gen3 USB2.0 host controller but with
few register sets. There is no PLL reset on the host side(USBCTR).
To address 1 and 3, I have modified the phy-rcar-gen2 with rz/g1c specific phy_ops .
Also added optional usb2.0 host reg property for initializing interrupt enable, OVC detection timer and Suspend/resume timer register .
I will send the patch based on the below discussion.
To address 2, I am seeing 2 solutions
solution 1) On the SoC dtsi->define USB1 clocks(ehci1/ohci1/hsusb1) and
On the board dts-> enable hsusb0 + usb1 host/peripheral.
solution 2) On the SoC dtsi->define USB1 clocks(ehci1/ohci1/hsusb1) followed by hsusb0 clock and
On the board dts-> enable only usb1 host/peripheral.
This will allow us to do pll reset without enabling hsusb0 on the board dts.
Do you have any preferences one way or the other? Or a third option?
Note:-
The board is populated with USB2.0 host on USB port 1 and USB2.0 function on USB Port0.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
