Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH] clocksource/drivers/sh_cmt: wait for CMCNT on init > > > What should we do next for fixing this error? Adding unconditional delays > also fixes the issue. > > I'd add 50 µs delays after the three register writes. It make sense to me as well, since the hardware manual is mentioning about inserting delays for the reliable counter operation. > > But I do not have the setup to verify this on gen1/gen2/gen3 variants. > > > > I have enabled CMT0/1/2/3 on R-Car M3-W Salvator-XS board and this issue > is not seen with original code. > > > > Only on R-Car Gen2/ RZ/G1, we are seeing this issue. > > As you can test on Koelsch, M3-W Salvator-XS, and RZ/G1, that should cover > most variants we care about. I will send a patch V2, after testing on all these variants. > CMT does not seem to be enabled on R-Car M1A and H1. > I'l do boot tests on older SH/R-Mobile SoCs as part of my general testing. > > > Note:- > > > > For R-Car M3-W board, inconsistency-check and nanosleep tests are > working fine. > > > > However there is a failure with clocksource_switch "asynchronous" test. > > The inconsistency-check is failing for "arch_sys_counter" after some > > clocksource_switch operations > > > > So I skipped the "clocksource_switching" for arch_sys_counter and > > the asynchronous test is passing for > > CMT0/1/2/3 timers. > > Sorry, being no timer expert, I don't understand the impact of the above > paragraph. We may start a discussion on this, when we start upstreaming CMT for R-Car M3-W devices. Basically clocksource_switch test in "selftests "uses 2 threads, In 1 thread it executes inconsistency-check test followed by nano sleep test and on the second thread it keep changing clock source one after the another. This test always fails on R-Car M3-W which is based on arm64. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
