On Mon, Oct 01, 2018 at 03:55:48PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Oct 1, 2018 at 3:36 PM Simon Horman <horms@xxxxxxxxxxxx> wrote:
> > On Fri, Sep 28, 2018 at 01:37:56PM +0200, Geert Uytterhoeven wrote:
> > > From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> > > This patch adds a device node for the Interrupt Controller for External
> > > Devices (INTC-EX) on R-Car E3, which serves external IRQ pins IRQ[0-5].
> > >
> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> > > ---
> > > Tested on Ebisu using IRQ1 and IRQ2 on CP49 and EXIO E.
> > > ---
> > > arch/arm64/boot/dts/renesas/r8a77990.dtsi | 16 ++++++++++++++++
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > index 5c1d6321a5d22a18..a175b5dd04ce3475 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > @@ -341,6 +341,22 @@
> > > #power-domain-cells = <1>;
> > > };
> > >
> > > + intc_ex: interrupt-controller@e61c0000 {
> > > + compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
> > > + #interrupt-cells = <2>;
> > > + interrupt-controller;
> > > + reg = <0 0xe61c0000 0 0x200>;
> > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
> > > + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
> > > + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
> > > + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
> > > + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
> > > + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 407>;
> >
> > I am struggling to locate the documentation for this clock,
> > although I do see it is consistent with (at least) the dtsi for H3.
>
> Unfortunately the INTC-* clocks were removed from the R-Car Gen3
> documentation, making it harder for DT to describe the hardware.
Understood, I will trust you on this one and apply this patch for v4.21.
