On Wed, Sep 19, 2018 at 04:50:42PM +0200, Geert Uytterhoeven wrote:
> PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> ---
> To be queued in clk-renesas-for-v4.20.
>
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 7e000d0705891a3f..9eb80180eea0b1a6 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
> /*
> * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
> *--------------------------------------------------------------------
> - * 0 48 x 1 x100/4 x100/3 x100/3
> - * 1 48 x 1 x100/4 x100/3 x58/3
> + * 0 48 x 1 x100/1 x100/3 x100/3
> + * 1 48 x 1 x100/1 x100/3 x58/3
> */
> #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
>
> --
> 2.17.1
>
