From: Simon Horman <horms+renesas@xxxxxxxxxxxx> Date: Tue, 18 Sep 2018 12:22:26 +0200 > From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@xxxxxxxxxxx> > > EtherAVB hardware requires 0 to be written to status register bits in > order to clear them, however, care must be taken not to: > > 1. Clear other bits, by writing zero to them > 2. Write one to reserved bits > > This patch corrects the ravb driver with respect to the second point above. > This is done by defining reserved bit masks for the affected registers and, > after auditing the code, ensure all sites that may write a one to a > reserved bit use are suitably masked. > > Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@xxxxxxxxxxx> > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx> I've decided to apply this to 'net', let me know if this is a problem.
