Hi Chris,
CC linux-clk
On Mon, Sep 17, 2018 at 8:57 PM Chris Brandt <Chris.Brandt@xxxxxxxxxxx> wrote:
> On Friday, September 14, 2018, Geert Uytterhoeven wrote:
> > > Just FYI, for the heck of it, I tried and hacked in registering the
> > > clock driver using CLK_OF_DECLARE since that happens before the
> > > TIMER_OF_DECLARE timers are probed.
> > >
> > > But, I got this result:
> > >
> > > [ 0.000000] Driver 'renesas-cpg-mssr' was unable to register with
> > bus_type 'platform' because the bus was not initialized.
> >
> > Indeed, you cannot register a platform device from CLK_OF_DECLARE().
> > Instead, you have to operate on the passed struct device_node pointer,
> > cfr. the old RZ/A1 clock driver.
>
> How about this proposal:
>
> I leave the current OSTM timer driver as it is today with
> TIMER_OF_DECLARE.
>
> But, I modify the clock driver so it registers a mini driver with
> CLK_OF_DECLARE that can enable individual HW module clocks using
> clk_register_fixed_rate. Once those modules/clocks are enabled, they are enabled
> forever.
>
> Also, later on when the full platform driver is probed, for any of those
> early clocks that were created, it basically ignores them.
>
>
> To use this early clock, you add this to your board's .dts file as such:
>
>
> /* Special Early CPG clocks */
> / {
> cpg_early: clock-controller@early {
> #clock-cells = <2>;
> compatible = "renesas,r7s9210-cpg-mssr-early";
> };
> };
>
> /* High resolution System tick timers */
> &ostm0 {
> status = "okay";
> clocks = <&cpg_early CPG_MOD 36>; /* replace .dtsi setting */
> power-domains = <&cpg_early>; /* replace .dtsi setting */
> };
> &ostm1 {
> status = "okay";
> clocks = <&cpg_early CPG_MOD 35>; /* replace .dtsi setting */
> power-domains = <&cpg_early>; /* replace .dtsi setting */
> };
>
>
> I've coded this up and it works fine.
While I don't doubt this works fine, your DT is no longer describing
hardware, but also software policy.
I think the proper solution, maximizing code reuse, is to:
- Split off early clocks from cpg_mssr_info.core_clks[] and .mod_clk[] into
cpg_mssr_info.early_core_clks[] and .early_mod_clks[],
- Split off early handling from cpg_mssr_probe(), to be called
a. from CLK_OF_DECLARE() in r7s9210-cpg-mssr.c, OR
b. from cpg_mssr_probe() if !cpg_mssr_info.early_core_clks.
BTW, this will also be needed for migrating other CA9-based SoCs to
renesas-cpg-mssr.c, as these don't have an ARM architectured timer,
just like RZ/A2.
Ideally (in the long term), Linux should learn to track dependencies properly,
so it initialized all components in the required order, automatically.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
