Hi Hoan,
On Fri, Sep 7, 2018 at 10:26 AM Nguyen An Hoan <na-hoan@xxxxxxxxxxx> wrote:
> From: Hoan Nguyen An <na-hoan@xxxxxxxxxxx>
>
> Add ZA2 clock support for the R8A77995 SoC
>
> Signed-off-by: Hoan Nguyen An <na-hoan@xxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -80,6 +80,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
>
> /* Core Clock Outputs */
> DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
> + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 10, 2),
(Why /10 * 2 instead of /5?)
ZA2 is not a fixed divider clock, but controlled through the ZA2 Clock
Control Register.
> DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
> DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
> DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
