RE: [PATCH] clk: renesas: cpg-mssr: Add R7S9210 support

[Chris Brandt <Chris.Brandt@xxxxxxxxxxx>]

Hi Geert,

Since my config for RZ/A2 does not set CONFIG_RESET_CONTROLLER, none of 
the reset code is built and cpg_mssr_reset_controller_register() just 
ends up being an empty function.

So basically my only change at this point is to make DTS and the module 
clock table use "36" instead of "306".

Are you OK with the idea of adding a macro ("STBCR_ID") in 
include/dt-bindings/clock/renesas-cpg-mssr.h?


DTS:
--------------------
	ostm0: timer@e803b000 {
		compatible = "renesas,r7s9210-ostm", "renesas,ostm";
		reg = <0xe803b000 0x30>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
		clocks = <&cpg CPG_MOD STBCR_ID(36)>;
		clock-names = "ostm0";
		power-domains = <&cpg>;
		status = "disabled";
	};



r7s9210-cpg-mssr.c:
--------------------
static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
	DEF_MOD("ostm0",	STBCR_ID(36),	R7S9210_CLK_P1C),
	DEF_MOD("ostm1",	STBCR_ID(35),	R7S9210_CLK_P1C),
	DEF_MOD("ostm2",	STBCR_ID(34),	R7S9210_CLK_P1C),


Thanks,
Chris