Hi Hoan,
On Fri, Aug 24, 2018 at 6:52 AM Nguyen An Hoan <na-hoan@xxxxxxxxxxx> wrote:
> From: Hoan Nguyen An <na-hoan@xxxxxxxxxxx>
>
> Signed-off-by: Hoan Nguyen An <na-hoan@xxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
> };
>
> static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> + DEF_MOD("fdp0", 119, R8A77965_CLK_S0D1),
In the datasheet, and in drivers for other SoCs, this clock is called fdp1-0.
> DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
> DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
> DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Will queue in clk-renesas-for-v4.20, with the clock name fixed, and a commit
message added (stolen from the r8a7796 commit ;-).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
