On 24/07/2018 15:26, Wolfram Sang wrote:
Hi Phil,
So, it is not possible to read SCL status then? Hmm, currently a working
get_scl is required...
...
Well, I don't know much about this IP core and how/where it is used. I
just wonder what happens if another user comes along using an
open-drain GPIO. Is that possible?
I assume it is the same with SDA? Non open-drain? Output only?
Just had a closer look at how it's setup here.
Maybe the following helps.
Thanks for the detailed explanation. I am just afraid it is a litle too
detailed for me. I am not sure if I can read it correctly:
When you read the SCL/SDA GPIO, does it return the true state of the
SCL/SDA line or does it just reflect the value it was set to output?
Yes it returns the true state of the output pin.
I admit it's a bit odd from the classic GPIO point of view.
There's no concept of HiZ internally in the FPGA.
Which probably means SDA is to be treated the same as SCL -> push/pull.
Yes. They're both driven push/pull, but the try state of the line is available.
If there was some kinda of OpenDrain gpio driver that modelled a FET
driven by a push pull GPIO I guess it could be made to work.
Still, that sounds quite unlikely to me, so we can for now assume that
all designware users will have push/pull?
I know of one other doing the same thing with the core in the Altera SocFPGA platform.
As they put me on to this solution for doing the recovery when the i2c was routed thru the SOC's fpga.
In other hard configurations they may have a 'proper' GPIO available that needs to be OpenDrain.
Disclaimer: I have zero experience with this core, I don't know how hard
it is to modify or which versions are out there.
--
Regards
Phil Reid
