On Fri, Jul 13, 2018 at 1:08 AM, Geert Uytterhoeven <geert+renesas@xxxxxxxxx> wrote: > R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or > Cortex-A15 CPU cores, all of which have ARM architectured timers. > > Force use of the ARM architectured timer on these SoCs. > This allows to: > - Remove the calls to shmobile_init_delay() from the corresponding > machine vectors, > - Remove a check in timer setup specific to R-Car Gen2, > - Remove a check in shmobile_init_delay(). > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- Hi Geert, Thanks for cleaning up stuff. > We still need shmobile_init_delay to setup loops-per-jiffies for the > other SoCs. But perhaps we can use the Cortex-A9 global timer on those? Perhaps unrelated, but on older kernels with Cortex-A9 the TWD timer was only available when using SMP. So historically on our single-core systems (with CA8 or CA9 or when using CA9 multi core with maxcpus=1) we had no timer available unless we also used a CMT/TMU or similar. Exactly what the level of software support is available for the ARM timers at this point I'm not so sure about. Cheers, / magnus
