Hello!
On 7/2/2018 4:03 PM, Geert Uytterhoeven wrote:
CC Sergei,
Thanks for your patch!
On Mon, Jul 2, 2018 at 10:06 AM Niklas Söderlund
<niklas.soderlund+renesas@xxxxxxxxxxxx> wrote:
The datasheet do not document any registers to control drive strength,
does
and no drive strength registers are for this reason described for this
SoC. The flag indicating that drive strength can be controlled are
flags
however set for some pins in the driver.
This leads to a NULL pointer dereference when the sh-pfc core tries to
access the struct describing the drive strength registers, for example
when reading the sysfs file pinconf-pins.
Fix this by removing the SH_PFC_PIN_CFG_DRIVE_STRENGTH from all pins.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
I'll wait a bit for Sergei's response.
Perhaps his version of the datasheet does document drive strength registers?
No, I have v1.00 which doesn't tell about drive control on V3M indeed.
MBR, Sergei
