On Thu, Jun 28, 2018 at 09:17:14AM +0100, Michel Pollet wrote: > Add a special enable method for the second CA7 of the R9A06G032 > as well as the default value for the "cpu-release-addr" property. > > Signed-off-by: Michel Pollet <michel.pollet@xxxxxxxxxxxxxx> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Thanks, applied. I had to manually resolve a conflict due to updates to the patch that added this dtsi file (as noted elsewhere). Please check that this is correct. From: Michel Pollet <michel.pollet@xxxxxxxxxxxxxx> Subject: [PATCH] ARM: dts: Renesas R9A06G032 SMP enable method Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: Michel Pollet <michel.pollet@xxxxxxxxxxxxxx> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> --- arch/arm/boot/dts/r9a06g032.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 339d0958011e..afe29c95a006 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -29,6 +29,8 @@ compatible = "arm,cortex-a7"; reg = <1>; clocks = <&sysctrl 84>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0 0x4000c204>; }; }; -- 2.11.0
