On 22/06/18 13:14, Geert Uytterhoeven wrote:
> Hi Michel,
>
> CC MarcZ
>
> On Thu, Jun 14, 2018 at 1:02 PM Michel Pollet
> <michel.pollet@xxxxxxxxxxxxxx> wrote:
>> This adds the Renesas R9A06G032 bare bone support.
>>
>> This currently only handles the SYSCTRL block note,
>> generic parts (gic, architected timer) and a UART.
>>
>> Signed-off-by: Michel Pollet <michel.pollet@xxxxxxxxxxxxxx>
>
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
>
>> + timer {
>> + compatible = "arm,cortex-a7-timer",
>
> Checkpatch says:
> WARNING: DT compatible string "arm,cortex-a7-timer" appears
> un-documented -- check ./Documentation/devicetree/bindings/
>
>> + "arm,armv7-timer";
>
> Documentation/devicetree/bindings/arm/arch_timer.txt says:
>
> compatible should at least contain "arm,armv7-timer"
>
> but fails to list other possible values?
The idea is that you could add something useful that matches your CPU.
Adding new CPU types in the binding seems to be a never ending battle...
>
>> + interrupt-parent = <&gic>;
>> + arm,cpu-registers-not-fw-configured;
Really? :-(
Thanks,
M.
--
Jazz is not dead. It just smells funny...
