> > Subject: Re: [PATCH] clocksource/drivers/sh_cmt: wait for CMCNT on
> > > diff --git a/drivers/clocksource/sh_cmt.c
> > > b/drivers/clocksource/sh_cmt.c index 70b3cf8..48910df 100644
> > > --- a/drivers/clocksource/sh_cmt.c
> > > +++ b/drivers/clocksource/sh_cmt.c
> > > @@ -328,7 +328,7 @@ static void sh_cmt_start_stop_ch(struct
> > > sh_cmt_channel *ch, int start)
> > >
> > > static int sh_cmt_enable(struct sh_cmt_channel *ch)
> > > {
> > > -int k, ret;
> > > +int j, k, ret;
> > >
> > > pm_runtime_get_sync(&ch->cmt->pdev->dev);
> > > dev_pm_syscore_device(&ch->cmt->pdev->dev, true); @@ -368,11
> > > +368,17 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch)
> > > * While at it, we're supposed to clear out the CMCNT as of this
> > > * moment, so make sure it's processed properly here. This will
> > > * take RCLKx2 at maximum.
> > > + *
> > > + * Similar register access usage for CMCNT is mentioned in R-Car
> > > + * Gen[2/3]/RZ/G1 user's manual, RCLKx2 for cmt0 and RCLKx2 or
> > > + * CPϕx2 (CPEXϕx2)) for cmt1.
> > > */
> > > -for (k = 0; k < 100; k++) {
> > > -if (!sh_cmt_read_cmcnt(ch))
> > > -break;
> > > -udelay(1);
> > > +for (j = 0; j < 2; j++) {
> > > +for (k = 0; k < 100; k++) {
> >
> > Why not simply count to 200 ISO 100?>
That also works. It needs delay more than 100.
The worst case wait is around 130-150 microseconds.
Previously, I have put a print statement just before break statement during debugging.
> This issue is related to settling of CMCNT register during init.
>
> During my testing, I found that the first loop exit immediately before actually
> settling this register value to "0". ie, the instantaneous value of register
> becomes "0" in the first check and it breaks the first loop and in the next
> check report the error.
>
> The new logic is to double check this register value and make sure that this
> register value is settled to "0", before starting the timer channel.
>
> Regards,
> Biju
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