On Tue, Jun 05, 2018 at 07:17:13PM +0200, Geert Uytterhoeven wrote: > Add a device node for the second Cortex-A53 CPU core on the Renesas > R-Car E3 (r8a77990) SoC, and adjust the interrupt delivery masks for ARM > Generic Interrupt Controller and Architectured Timer. > > Based on a patch in the BSP by Takeshi Kihara. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- > Note that the PSCI implementation on Ebisu may be a preliminary version > with some familiar quirks: > - SMP bringup works, and both CPUs can be used, > - CPU1 can be offlined, but trying to bring it online again crashes > the system. > > I'm confident this will be fixed in future firmware versions, just like > on H3/Salvator-X. Thanks Geert, applied.
