Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: Michel Pollet <michel.pollet@xxxxxxxxxxxxxx> --- arch/arm/boot/dts/r9a06g032.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 9534f1b..d7b5414 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -30,6 +30,8 @@ compatible = "arm,cortex-a7"; reg = <1>; clocks = <&sysctrl R9A06G032_DIV_CA7>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0x4000c204>; }; }; -- 2.7.4
