Hi Simon,
On Sun, May 13, 2018 at 10:14 AM, Simon Horman <horms@xxxxxxxxxxxx> wrote:
> On Fri, May 11, 2018 at 01:31:18PM +0900, Yoshihiro Shimoda wrote:
>> This patch adds PFC device node for r8a77990 (R-Car E3).
>>
>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
>> index 4658029..efc3c0b 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
>> @@ -60,6 +60,11 @@
>> #size-cells = <2>;
>> ranges;
>>
>> + pfc: pin-controller@e6060000 {
>> + compatible = "renesas,pfc-r8a77990";
>> + reg = <0 0xe6060000 0 0x508>;
>> + };
>
> Here the register size is 0x508 which matches r8a77995.dtsi in mainline.
> Other variants there are:
> * 0x50c: r8a7795.dtsi, r8a77965.dtsi, r8a7796.dtsi
> * 0x504: r8a77970.dtsi
The number of registers is SoC-specific.
R-Car H3, M3-W, and M3-N share PFC documentation.
> My reading of the documentation is that the size of the register range is
> 0x50c. So I suggest we either use that value consistently or move to a
> larger value after some rounding-up. Geert?
According to Section 6D ("Pin Function Controller (PFC)" for R-Car E3)
of the datasheet, the last register is at offset 0x504, so length 0x508 is
correct.
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
