Re: [PATCH v2 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions

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On Fri, Apr 20, 2018 at 09:27:43PM +0900, Yoshihiro Shimoda wrote:
> From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> 
> This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
> 
> Note that internal CPG clocks (S0, S1, S2, S3, SDSRC) are not included,
> as they are used as internal clock sources only, and never referenced
> from DT.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> [shimoda: add SPDX-License-Identifier]
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> ---
>  include/dt-bindings/clock/r8a77990-cpg-mssr.h | 62 +++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>



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