On Thu, Mar 29, 2018 at 07:33:05PM +0200, Geert Uytterhoeven wrote: > Hi all, > > The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where > the LB clock divider depends on the value of the MD18 pin. > > However, on most RZ/G1 and R-Car Gen2 SoCs, the LB clock divider is > fixed to 24. Hence this series corrects the LB clock on affected SoCs > by modelling it as a fixed factor clock instead. > > This doesn't have much impact, as no kernel code relies on the rate of > the LB clock. > > To be queued in clk-renesas-for-v4.18. Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
