On Fri, Mar 23, 2018 at 09:41:29AM +0100, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Mar 22, 2018 at 11:24 AM, Simon Horman > <horms+renesas@xxxxxxxxxxxx> wrote: > > Sort subnodes of the soc node. > > - The primary key is the bus address. > > - The secondary key is the IP block. > > - The tertiary key is the node name. > > > > This is part of an ongoing effort to provide consistent node > > order in the DT of Renesas SoCs to improve maintainability. > > > > This should not have any run-time effect. > > > > Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx> > > --- > > v2 > > * Rebase > > Thanks for the update! > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > using dtx_diff, and "grep '@.*{', which tells me > > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > pciec0: pcie@fe000000 { > > @@ -2097,6 +2090,23 @@ > > status = "disabled"; > > }; > > > > + gic: interrupt-controller@f1010000 { > > Probably gic should be before pciec0. > Currently it's after pciec1, which has a lower address than pciec1. Thanks, I will fix this in v3.