Re: [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting

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Simon,

sorry for the delay in checking this. I refreshed my memory about the
issues here this evening and will be able to do educated tests tomorrow.

However, one question already:

> - In M3N, HS400 mode and HS200 mode use the same clock setting.

a) I did not find any code handling this speciality for M3N, neither
   here nor in the SDHI driver. Did you notice something in the BSP?

b) do you know the reasons for this? Looking at the datasheet I have,
   sdsrc is 800MHz for all Gen3 SoC.

> On H3 ES1.0 / Salvator-X I do not see any problems either with or without
> this patch.

I assume this is because the speed is 200MHz instead of 400MHz. The
sdsrc clk is half speed on Salvator-X-H3-ES1.0. I hope I can confirm my
assumption tomorrow.

> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/hs400-v2

Thanks, that was useful!

Regards,

   Wolfram

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