This patch adds ZG clock divider support for R-Car Gen3 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@xxxxxxxxx>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 5 +++++
drivers/clk/renesas/rcar-gen3-cpg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index a7d68ce..cfbefcc 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -76,6 +76,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
#define CPG_FRQCRC 0x000000e0
#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
+#define CPG_FRQCRC_ZGFC_MASK GENMASK(28, 24)
struct cpg_z_clk {
struct clk_hw hw;
@@ -563,6 +564,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
return cpg_z_clk_register(core->name, __clk_get_name(parent),
base, CPG_FRQCRC_Z2FC_MASK);
+ case CLK_TYPE_GEN3_ZG:
+ return cpg_z_clk_register(core->name, __clk_get_name(parent),
+ base, CPG_FRQCRC_ZGFC_MASK);
+
default:
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index ea4f8fc..3ae9fe6d 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -23,6 +23,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PE,
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
+ CLK_TYPE_GEN3_ZG,
};
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
--
2.7.4
