From: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU cores are driven by the same clock. Add the missing clocks properties to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Tested-by: Simon Horman <horms+renesas@xxxxxxxxxxxx> Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx> --- arch/arm/boot/dts/r8a7790.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index f247beb3863f..e85eb42f97e8 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; @@ -82,6 +83,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; @@ -92,6 +94,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; -- 2.11.0
