Hi Simon, Fabrizio,
On Fri, Sep 15, 2017 at 9:45 AM, Simon Horman <horms@xxxxxxxxxxxx> wrote:
> On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
>> From: Fabrizio Castro <fabrizio.castro@xxxxxxxxxxxxxx>
>>
>> Add DT node for the Advanced Power Management Unit (APMU), add the
>> second CPU core, and use "renesas,apmu" as "enable-method".
>>
>> Signed-off-by: Fabrizio Castro <fabrizio.castro@xxxxxxxxxxxxxx>
>> Signed-off-by: Chris Paterson <chris.paterson2@xxxxxxxxxxx>
>> ---
>> This patch is based on renesas-devel-20170913-v4.13.
>
> Hi,
>
> with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
> is the CNTVOFF initialised in the boot loader of boards (in upstream)
> for this SoC? If not I expect you will have trouble with the arch timer
> on secondary CPU cores.
Exactly my question.
Fabrizio: Given your feedback on "[PATCH v3 0/3] ARM: renesas: Enable SMP on
R-Car E2", I think SMP enablement on RZ/G1E has to be postponed until "ARM:
shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15" has been
accepted upstream.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
