On Mon, Apr 03, 2017 at 11:45:40AM +0200, Geert Uytterhoeven wrote: > Hi Simon, Magnus, Morimoto-san, > > The SSI-ALL gate clock is located in between the P clock and the > individual SSI[0-9] clocks, hence the former should be listed as their > parent. > > This patch series corrects the parents in the DTSes r8a7790, r8a7791, > and r8a7793. The DTS for r8a7794, and the CPG/MSSR-based clock drivers > for r8a7743, r8a7745, and r8a7795 already describe the correct parent. > > Thanks! Thanks, I have queued these up.
