Re: [PATCH 1/1] clk: renesas: cpg-mssr: r8a7796: add IMR clocks

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Hi Sergei,

On Tue, Feb 21, 2017 at 7:54 PM, Sergei Shtylyov
<sergei.shtylyov@xxxxxxxxxxxxxxxxxx> wrote:
> On 02/20/2017 11:38 AM, Geert Uytterhoeven wrote:
>>> Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
>>>
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>>
>>> --- linux.orig/drivers/clk/renesas/r8a7796-cpg-mssr.c
>>> +++ linux/drivers/clk/renesas/r8a7796-cpg-mssr.c
>>> @@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796
>>>         DEF_MOD("vin1",                  810,   R8A7796_CLK_S0D2),
>>>         DEF_MOD("vin0",                  811,   R8A7796_CLK_S0D2),
>>>         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
>>> +       DEF_MOD("imr1",                  822,   R8A7796_CLK_S2D1),
>>> +       DEF_MOD("imr0",                  823,   R8A7796_CLK_S2D1),
>>
>>
>> According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent
>> clock is S0D2, like on H3 ES2.0.
>
>    Not S0D4? I'd expect that what they call "register access" to be
> controlled by the MSSR bits...

Good question...

>> Will queue in clk-renesas-for-v4.12 with corrected parent clock.
>
>    So, what have you used for 7795 and 7796?

S2D1 for r8a7795 (H3 ES1.0)
S0D2 for r8a7796 (M3-W)

And I planned to use S0D2 for H3 ES2.0, too.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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