Re: [PATCH/RFC] clk: renesas: r8a7795: Replace PLL3 multiplication setting

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Hi Kaneko-san,

On Sun, Feb 12, 2017 at 6:35 PM, Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
>
> This patch replaces PLL3 multiplication setting for DDR clock frequency.
>
>   - After changes, new PLL3 multiplication setting:
>     MD19 MD17 : DDR clock frequency
>     -------------------------------
>       0    0  : DDR3200
>       0    1  : DDR2800
>       1    0  : DDR2400
>       1    1  : DDR1600
>
>   - Before changes, old PLL3 multiplication setting:
>     MD19 MD17 : DDR clock frequency
>     -------------------------------
>       0    0  : DDR3200
>       0    1  : DDR2133
>       1    0  : Prohibited setting
>       1    1  : DDR1600
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx>

JFTR, this patch, and its counterpart for r8a7796, are too experimental
for upstream.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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