Hi Jacopo, Thanks for the patches. On Wednesday, January 25, 2017, Jacopo Mondi wrote: > Right now, the only "SoC" module support implemented is for RZ/A1H (Genmai > and GR-Peach boards). I'm going to give it a try on the RZ/A1 RSK board. > I have tested the correctness of mux settings printing out register values, > and enabling/disabling the SCIF2 module connected to serial debug > interface. I can give it a try on things like Eth, I2C, SPI, SDHI, MMC. > One note on the current DT ABI: > right now a pin configuration is specified in DTS using utility macros > defined in the (currently undocumented) arch/arm/boot/dts/include/dt- > bindings/pinctrl/pinctrl-renesas-rz.h header file. > Each pin configuration is a triplet of u32 in the form of > > <BANK PIN ALTERNATE_FUNC_#> > > It should be fairly easy adding additional parameters to configure what > was missing in the original group-based PFC driver for RZ devices (I'm > thinking of IO mode control, input buffer configuration, bi-directional > configuration etc). SDHI is one that will need another parameter. Half the pins need Bidirection (PBDC) enabled, and the other half need PBDC disabled. SDHI data pins are PBDC=1, the others are PBDC=0. > The series makes use of newly introduced pin[ctrl|mux]_generic functions, > currently only available in Linus Walleij's linux-pinctrl.git tree. Hmmm, I was hoping to 'easily' back port this to 4.9. I guess if it's the best way forward, then maybe I can back port those new generic functions for the LTSI tree. Chris
