Hello Renesas SoC people, One difference between R-Car/RZG vs RZA is that there is no status bits for the MSTP clocks. This means even though you enable a clock by clearing the module-stop bit, you're not really guaranteed that the peripheral block is ready to be used. For the most part, the register interface is accessible, but usage of the HW might not be fully ready. Now that clock enable/disable has been fixed for RZ/A1 and actually works, you can start to see things break. For RZ/A1 (r7s72100) you can see this for the I2C driver (i2c-riic.c) and SPI driver (spi-rspi.c). Both of these drivers disable the clock in between EVERY TRANSFER as a means of runtime pm. Since SDHI (tmio) needs to keep the clock running for the card detect logic, it does not implement runtime pm, so it's OK. The only way to really fix this for RZ/A1 is to put an arbitrary delay in the clk-mstp.c driver: spin_lock_irqsave(&group->lock, flags); value = cpg_mstp_read(group, group->smstpcr); if (enable) value &= ~bitmask; else value |= bitmask; cpg_mstp_write(group, value, group->smstpcr); spin_unlock_irqrestore(&group->lock, flags); + if (enable || !group->mstpsr) + udelay(100); + if (!enable || !group->mstpsr) return 0; Or, just remove runtime PM for RZ/A1. * i2c-riic.c: This driver is just for the RZ/A series, so just remove runtime pm completely * spi-rspi.c: Disable runtime pm just for RZ/A series parts Therefore, before I start firing off patches to remove runtime PM for RZ/A, does anyone have an opinion one way of the other???? Regards, Chris
