Re: [PATCH v2 2/3] arm64: renesas: r8a7796: Add all SCIF nodes

[Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>]

Hello!

On 12/7/2016 7:44 PM, Ulrich Hecht wrote:

> Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks
> and clock domain.

   Not power domain?

> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@xxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
>  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 65 ++++++++++++++++++++++++++++++++
>  1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> index 7bf0f2f..c5f0df5 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -421,6 +421,32 @@
>  			};
>  		};
>
> +		scif0: serial@e6e60000 {
> +			compatible = "renesas,scif-r8a7796",
> +				     "renesas,rcar-gen3-scif", "renesas,scif";
> +			reg = <0 0xe6e60000 0 64>;

    0x40, perhaps?

> +			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 207>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		scif1: serial@e6e68000 {
> +			compatible = "renesas,scif-r8a7796",
> +				     "renesas,rcar-gen3-scif", "renesas,scif";
> +			reg = <0 0xe6e68000 0 64>;

   Same here...

> +			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 206>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
>  		scif2: serial@e6e88000 {
>  			compatible = "renesas,scif-r8a7796",
>  				     "renesas,rcar-gen3-scif", "renesas,scif";
> @@ -434,6 +460,45 @@
>  			status = "disabled";
>  		};
>
> +		scif3: serial@e6c50000 {
> +			compatible = "renesas,scif-r8a7796",
> +				     "renesas,rcar-gen3-scif", "renesas,scif";
> +			reg = <0 0xe6c50000 0 64>;

   And here...

> +			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 204>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		scif4: serial@e6c40000 {
> +			compatible = "renesas,scif-r8a7796",
> +				     "renesas,rcar-gen3-scif", "renesas,scif";
> +			reg = <0 0xe6c40000 0 64>;

   And here...

> +			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 203>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		scif5: serial@e6f30000 {
> +			compatible = "renesas,scif-r8a7796",
> +				     "renesas,rcar-gen3-scif", "renesas,scif";
> +			reg = <0 0xe6f30000 0 64>;

   And here...

> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 202>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
>  		msiof0: spi@e6e90000 {
>  			compatible = "renesas,msiof-r8a7796";
>  			reg = <0 0xe6e90000 0 0x0064>;

MBR, Sergei