Re: R-Car gen3 PLL0/2/4 frequencies incorrect?

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Hi Sergei,

On Sun, Oct 30, 2016 at 7:36 PM, Sergei Shtylyov
<sergei.shtylyov@xxxxxxxxxxxxxxxxxx> wrote:
> drivers/clk/renesas/rcar-gen3-cpg.c seems to forget that the PLL0/2/4 all
> have a fixed divisor (2) while it multiplies PLLxCR.STC with 2 for the
> 'mult' variable (see the manual). All the dependent frequencies this should
> be reported greater x2 than the actual ones...

The actual frequencies in /sys/kernel/debug/clk/clk_summary are correct, though,
considering MD14=MD13=MD19=M17=1 (for a 33.3333 MHz EXTAL), while
Salvator-X has a 16.6666 MHz EXTAL.

Perhaps you missed the extal divider?

Note that I have measured MSIOF clock signal frequencies before, and they
matched Linux' point of view.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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