On 10/20/2016, Wolfram Sang wrote: > Sadly, I don't have SDHI documentation for this SoC. In the current hardware manual on renesas.com, the SHDI section is not included. However, for version 3.0 that will be posted shortly, it will start to include the SDHI section. > * Does it have a version register (CTL_VERSION)? If so, what does it > say? 0x820B > * Does it have SD_BUF0 width setting (named either EXT_ACC or HOST_MODE, > so far always comes after the version register)? If so, what is its > layout? There is a "EXT_SWAP" register. It is the only thing after VERSION. VERSION = 0xE804E0E2 EXT_SWAP = 0xE804E0F0 Here are the bits in that register: DMASE (bit 8) DMA Transfer Size Select Selects the transfer unit for SD_BUF read/write DMA transfer. Set this bit in combination with the transfer size set in the DMA Channel Configuration register. 0: 4-byte (longword) unit 1: 64-byte (longword 16) unit SDBRSWAP (bit 7) SD_BUF0 Swap Read*1 When reading from SD_BUF0, data stored in SD_BUF0 can be replaced and then read.*2 0: The current data is read without replacement. 1: Data replacement for reading proceeds in bytes SDBWSWAP (bit 6) SD_BUF0 Swap Write*1 When writing to SD_BUF0, data to be written can be replaced and then stored in SD_BUF0.*2 0: The current data is written without replacement. 1: Data replacement for writing proceeds in bytes. > * Does it support DMA? Yes. > Is it compatible to the current implementation? I don't know yet. The current BSP is on 3.14 and it uses DMA, but I'm not sure what's going to happen as I start moving things to 4.9+. > > + /* if count was multiple of 4 */ > > + if (!(count & 0x3)) > > + return; > > + buf8 = (u8 *)(buf + (count >> 2)); > > + count %= 4; > > To skip the same operation done on 'count' twice, maybe? > > buf8 = (u8 *)(buf + (count >> 2)); > count &= 3; > > if (!count) > return; That looks like it should work. I can try it out and see if there is something we are missing. Thanks Chris
