RGB LVDS BRIDGE SUPPORT IN RCAR E2

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hi,
  I would like to give support to RGB LVDS BRIDGE  RCAR E2 

  I am attaching the patch file..can you please review it and let me know the status.is it correct or not?





 
Best Regards
 Jithin T Raj
 
   
diff --git a/a/r8a7794-alt.dts b/b/r8a7779-marzen.dts
index 383ad79..b795da6 100644
--- a/a/r8a7794-alt.dts
+++ b/b/r8a7779-marzen.dts
@@ -1,7 +1,8 @@
 /*
- * Device Tree Source for the Alt board
+ * Device Tree Source for the Marzen board
  *
- * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
@@ -9,29 +10,64 @@
  */
 
 /dts-v1/;
-#include "r8a7794.dtsi"
+#include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
-	model = "Alt";
-	compatible = "renesas,alt", "renesas,r8a7794";
+	model = "marzen";
+	compatible = "renesas,marzen", "renesas,r8a7779";
 
 	aliases {
 		serial0 = &scif2;
+		serial1 = &scif4;
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
-		stdout-path = "serial0:115200n8";
+		bootargs = "ignore_loglevel root=/dev/nfs ip=on";
+		stdout-path = &scif2;
 	};
 
-	memory@40000000 {
+	memory {
 		device_type = "memory";
-		reg = <0 0x40000000 0 0x40000000>;
+		reg = <0x60000000 0x40000000>;
 	};
 
-	lbsc {
-		#address-cells = <1>;
-		#size-cells = <1>;
+	fixedregulator3v3: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	ethernet@18000000 {
+		compatible = "smsc,lan9220", "smsc,lan9115";
+		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&ethernet_pins>;
+		pinctrl-names = "default";
+
+		phy-mode = "mii";
+		interrupt-parent = <&irqpin0>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		smsc,irq-push-pull;
+		reg-io-width = <4>;
+		vddvario-supply = <&fixedregulator3v3>;
+		vdd33a-supply = <&fixedregulator3v3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		};
+		led3 {
+			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		};
+		led4 {
+			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+		};
 	};
 
 	vga-encoder {
@@ -43,13 +79,13 @@
 
 			port@0 {
 				reg = <0>;
-				adv7123_in: endpoint {
-					remote-endpoint = <&du_out_rgb1>;
+				vga_enc_in: endpoint {
+					remote-endpoint = <&du_out_rgb0>;
 				};
 			};
 			port@1 {
 				reg = <1>;
-				adv7123_out: endpoint {
+				vga_enc_out: endpoint {
 					remote-endpoint = <&vga_in>;
 				};
 			};
@@ -61,21 +97,36 @@
 
 		port {
 			vga_in: endpoint {
-				remote-endpoint = <&adv7123_out>;
+				remote-endpoint = <&vga_enc_out>;
 			};
 		};
 	};
 
-	x2_clk: x2-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <74250000>;
+	lvds-encoder {
+		compatible = "thine,thc63lvdm83d";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				lvds_enc_in: endpoint {
+					remote-endpoint = <&du_out_rgb1>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				lvds_connector: endpoint {
+				};
+			};
+		};
 	};
 
-	x13_clk: x13-clock {
+	x3_clk: x3-clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <148500000>;
+		clock-frequency = <65000000>;
 	};
 };
 
@@ -84,22 +135,33 @@
 	pinctrl-names = "default";
 	status = "okay";
 
-	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
-		 <&mstp7_clks R8A7794_CLK_DU0>,
-		 <&x13_clk>, <&x2_clk>;
-	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+	clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
+	clock-names = "du", "dclkin.0";
 
 	ports {
+		port@0 {
+			endpoint {
+				remote-endpoint = <&vga_enc_in>;
+			};
+		};
 		port@1 {
 			endpoint {
-				remote-endpoint = <&adv7123_in>;
+				remote-endpoint = <&lvds_enc_in>;
 			};
 		};
 	};
 };
 
+&irqpin0 {
+	status = "okay";
+};
+
 &extal_clk {
-	clock-frequency = <20000000>;
+	clock-frequency = <31250000>;
+};
+
+&tmu0 {
+	status = "okay";
 };
 
 &pfc {
@@ -107,152 +169,83 @@
 	pinctrl-names = "default";
 
 	du_pins: du {
-		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
-		function = "du";
-	};
-
-	scif2_pins: serial2 {
-		groups = "scif2_data";
-		function = "scif2";
+		du0 {
+			groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
+			function = "du0";
+		};
+		du1 {
+			groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
+			function = "du1";
+		};
 	};
 
 	scif_clk_pins: scif_clk {
-		groups = "scif_clk";
+		groups = "scif_clk_b";
 		function = "scif_clk";
 	};
 
-	ether_pins: ether {
-		groups = "eth_link", "eth_mdio", "eth_rmii";
-		function = "eth";
+	ethernet_pins: ethernet {
+		intc {
+			groups = "intc_irq1_b";
+			function = "intc";
+		};
+		lbsc {
+			groups = "lbsc_ex_cs0";
+			function = "lbsc";
+		};
 	};
 
-	phy1_pins: phy1 {
-		groups = "intc_irq8";
-		function = "intc";
+	scif2_pins: serial2 {
+		groups = "scif2_data_c";
+		function = "scif2";
 	};
 
-	i2c1_pins: i2c1 {
-		groups = "i2c1";
-		function = "i2c1";
+	scif4_pins: serial4 {
+		groups = "scif4_data";
+		function = "scif4";
 	};
 
-	vin0_pins: vin0 {
-		groups = "vin0_data8", "vin0_clk";
-		function = "vin0";
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		function = "sdhi0";
 	};
-};
 
-&cmt0 {
-	status = "okay";
-};
-
-&pfc {
-	qspi_pins: spi0 {
-		groups = "qspi_ctrl", "qspi_data4";
-		function = "qspi";
+	hspi0_pins: hspi0 {
+		groups = "hspi0";
+		function = "hspi0";
 	};
 };
 
-&ether {
-	pinctrl-0 = <&ether_pins &phy1_pins>;
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";
 
-	phy-handle = <&phy1>;
-	renesas,ether-link-active-low;
 	status = "okay";
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-		interrupt-parent = <&irqc0>;
-		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
-		micrel,led-mode = <1>;
-	};
 };
 
-&i2c1 {
-	pinctrl-0 = <&i2c1_pins>;
+&scif4 {
+	pinctrl-0 = <&scif4_pins>;
 	pinctrl-names = "default";
 
 	status = "okay";
-	clock-frequency = <400000>;
-
-	composite-in@20 {
-		compatible = "adi,adv7180";
-		reg = <0x20>;
-		remote = <&vin0>;
-
-		port {
-			adv7180: endpoint {
-				bus-width = <8>;
-				remote-endpoint = <&vin0ep>;
-			};
-		};
-	};
 };
 
-&vin0 {
+&scif_clk {
+	clock-frequency = <14745600>;
 	status = "okay";
-	pinctrl-0 = <&vin0_pins>;
-	pinctrl-names = "default";
-
-	port {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		vin0ep: endpoint {
-			remote-endpoint = <&adv7180>;
-			bus-width = <8>;
-		};
-	};
 };
 
-&scif2 {
-	pinctrl-0 = <&scif2_pins>;
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
 
+	vmmc-supply = <&fixedregulator3v3>;
+	bus-width = <4>;
 	status = "okay";
 };
 
-&scif_clk {
-	clock-frequency = <14745600>;
-	status = "okay";
-};
-
-&qspi {
-	pinctrl-0 = <&qspi_pins>;
+&hspi0 {
+	pinctrl-0 = <&hspi0_pins>;
 	pinctrl-names = "default";
-
 	status = "okay";
-
-	flash@0 {
-		compatible = "spansion,s25fl512s", "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <30000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
-		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "loader";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "system";
-				reg = <0x00040000 0x00040000>;
-				read-only;
-			};
-			partition@80000 {
-				label = "user";
-				reg = <0x00080000 0x03f80000>;
-			};
-		};
-	};
 };

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