On Thu, Sep 15, 2016 at 1:19 PM, Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
> On Wed, Sep 14, 2016 at 6:45 PM, Ulrich Hecht
> <ulrich.hecht+renesas@xxxxxxxxx> wrote:
>> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@xxxxxxxxx>
>> ---
>> drivers/clk/renesas/r8a7796-cpg-mssr.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
>> index eb347ed..c02fe34 100644
>> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
>> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
>> @@ -109,6 +109,9 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
>> };
>>
>> static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
>> + DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
>> + DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
>> + DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S3D1),
>
> It's not clear from the documentation what the actual parent clock is.
> The datasheet says "ZS", which we know is S3D1 on H3.
> However, Table 50.2 says ZS is S0D3 on M3-W (and H3 ES2.0)....
Queuing in clk-renesas-for-v4.10 with parent clock fixed to S0D3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
